Web site: www.lac.inpe.br/~celso/pad/multi.html
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Mulplix – a Unix-like operating system designed to support medium-grain parallelism and to provide an efficient environment for running parallel applications within MULTIPLUS.
MULTIPLUS is a distributed shared-memory multiprocessor designed to have a modular architecture which is able to support up to 1024 processing elements and 32 Gbytes of global memory address space. Within MULTIPLUS, up to four processing elements can be interconnected through a 64-bit double-bus system making up a cluster. The MULTIPLUS NUMA (Non-Uniform Memory Access) architecture supports up to 256 clusters interconnected through an inverted n-cube multistage network and uses a distibuted I/O system architecture.
The MULTIPLUS project has been under development at NCE/UFRJ (Federal University of Rio de Janeiro (UFRJ), at the Electronic Computing Center (NCE), Brazil) for some years now and has provided a nice and challenging framework for research work in several areas related to the world of High-Performance Computing: Parallel Architectures, Operating Systems, IC Design, Parallel Programming Environments and Parallel Algorithms. This short paper presents the current status of the project under development within the FINEP Academic PAD Program.
The mainstream of the research efforts in the area of IC design within the MULTIPLUS/MULPLIX project is the design of NCESPARC, a 32-bit RISC microprocessor, using CMOS 1.0u technology. The NCESPARC architecture follows the SPARC version 7.0 definition. The 32-bit Data Path consists of a three-port Register File, an ALU, a Barrel Shifter and auxiliary registers.
The architecture is implemented as a four-stage pipeline: fetch; decoding and operand fetching; execution; and writing of the result in the register file. For each pipeline stage, there is an instruction register associated with it which stores the code of the instruction under processing at that stage. For each pipeline stage, a set of logic equations describe the control logic which has been implemented using the standard-cell appproach.
In addition, to the design of the NCESPARC microprocessor, a CMOS implementation of the MULTIPLUS bus arbiters [Barb96] has been performed using CMOS 1.0u technology. This chip has been tested after fabrication and has performed according to the specifications.